In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to avoid that the presence of a limited number of defective memory elements on many millions forces the rejection of the entire chip, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number of additional memory elements, commonly called "redundancy memory elements", to be used as a replacement of those elements that, during testing of the memory device, prove defective; the selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry", while the set of redundancy memory elements and circuitry is defined for short as "redundancy".
The redundancy circuitry comprises programmable non-volatile memory registers suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy, both rows ("word lines") and columns ("bit lines") of redundancy memory elements are provided in the memory matrix; each redundancy word line or bit line is associated to a respective non-volatile memory register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected.
As far as matrix word lines are concerned, it has been recognized that the most frequent defect consists in short-circuits between adjacent word lines: this situation is easily detected during testing because when the selection of one of two short-circuited word lines is attempted, the potential of such word line cannot raise to the designed value, being linked by the short-circuit to the potential of the adjacent non-selected word line. When during testing a matrix word line is found that is short-circuited to an adjacent one, both of the two defective matrix word lines must be replaced by two redundancy word lines; from then on the two defective matrix word lines will never be selected, neither during programming nor during reading.
The implementation of word line redundancy in Flash Electrically Erasable Programmable ROM devices (shortly, Flash EEPROMs) poses some problems. Flash EEPROM devices are characterized by being not only electrically programmable, but also electrically erasable; as EPROM devices, they are programmed on a per-byte basis, raising to a high voltage (typically 12 V) the selected word line; erasing is instead a bulk operation, performed on the whole memory matrix, or at least on sectors of it, by switching the common source line of the memory matrix to the high voltage, while keeping all the word lines to ground. To prevent memory elements which are already in the non-programmed condition from being overerased, with the unacceptable consequence of obtaining, after the erasure, memory elements with negative threshold voltages, it is necessary to carry out a preliminary programming step of all the memory elements in the memory matrix, or in the matrix sector that is to be erased. In this way, all the memory elements are put in a common starting condition, so that after erasure all the memory elements have approximately the same threshold voltage. Such preliminary programming is called "preprogramming" or "preconditioning".
Preprogramming, similarly to normal programming, is performed on a per-byte basis, sequentially addressing the word lines of the memory matrix. This implies that, if defective word lines which have been replaced by redundancy word lines exist, since when such defective word lines are addressed the redundancy circuitry generates a deselection signal that prevents the defective word lines from being selected, the memory elements connected to them can never be preprogrammed; on the other hand, since erasure does not require the selection of the word lines, the memory elements connected to defective word lines are subjected to erasure. This means that, if the traditional word line redundancy approach is utilized in a Flash EEPROM device, the memory elements connected to defective word lines are destined to acquire more and more negative threshold voltages.
To overcome such a problem, the word line redundancy approach utilized in Flash EEPROMs provides for the inhibition of the defective word line deselection signal, generated by the redundancy circuitry, when, during preprogramming, a defective word line is addressed: in this way, when during preprogramming a defective word line is addressed, the memory elements connected to it can be effectively programmed.
This however requires not only the currently addressed defective word line is effectively selected, but also the selection of an adjacent word line: since in fact it is assumed that the defective word line is short-circuited to an adjacent word line, if said adjacent word line is not selected and its potential is kept to ground, the potential of the addressed defective word line cannot raise to the designed value necessary for the programming of the memory elements (12 V); in other words, two adjacent word lines that are short-circuited one to another must be simultaneously selected during preprogramming.
This requirement is responsible of a significant increase in complexity of the word line address decoding and selection circuitry, which means an increase in the overall chip size.